Semiconductor device with dram cell and method of manufacturing the same

ABSTRACT

A semiconductor device including a semiconductor substrate a trench forming in the substrate, an insulating film forming on an inner surface of the trench so as to be rendered thicker from a substrate surface side thereof toward a trench deep side thereof, and an electrode layer forming inside the insulating film forming inside the trench so as to extend from a trench deep part side toward the surface side of the substrate. The substrate surface side of the insulating film functions as a collar insulating film retaining an insulation performance between the electrode layer and the semiconductor substrate, and the trench deep side of the insulating film functions as a capacitor insulating film composing a capacitor of a DRAM cell.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a divisional of U.S. application Ser. No.11/235,210, filed Sep. 27, 2005, and is based upon and claims thebenefit of priority from the prior Japanese Patent Application No.2004-281936, filed on Sep. 28, 2004, the entire contents of each ofwhich are incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the invention

The present invention relates to a semiconductor device provided with aDRAM cell having a trench capacitor and a method of manufacturing thesemiconductor device.

2. Description of the related art

A dynamic random access memory (DRAM) cell provided with a trenchcapacitor comprises a semiconductor substrate formed with a deep trenchand a capacitor formed in a deep inside of the trench. Regarding thecapacitor, a capacitor insulating film is formed on a deep insidesurface of the trench. A first electrode layer is buried inside thecapacitor insulating film, whereby the capacitor is fabricated.Furthermore, a second electrode layer is formed on the first electrodelayer. A collar insulating film is formed in order to retain aninsulation performance between the semiconductor substrate and the firstand second electrode layers buried inside the trench.

JP-A-2003-60079 discloses a capacitor manufacturing method. In thedisclosed method, a capacitor insulating film, collar insulating filmand electrode layer are formed in a trench as follows. Firstly, a deeptrench (corresponding to a trench) is formed in a substrate(corresponding to a semiconductor substrate). Subsequent to severalsteps, a capacitor dielectric layer (corresponding to a capacitorinsulating film) is formed on an inner surface of the deep trench. Aconductive layer (corresponding to an electrode layer) is formed so asto fill the deep trench. At this time, a gap occurs in the conductivelayer. Subsequently, a part of the conductive layer corresponding to anupper portion of the deep trench is removed while a part of theconductive layer corresponding to a bottom of the deep trench.

Furthermore, a colored oxidation layer (corresponding to a collarinsulating film) is formed and a colored liner layer made of a materialdiffering from the colored oxidation layer is also formed. A partcorresponding to the upper conductive layer is removed. In this case, anoxide is present in the gap. Accordingly, when the conductive layer isformed on the gap, there is a possibility that electric connectioncannot be obtained. In view of the possibility, the colored oxidationlayer of a part corresponding to the gap is removed.

In the manufacturing method of JP-A-2003-60079, the capacitor dielectriclayer is formed as the capacitor insulating film, and the coloredoxidation layer and colored liner layer are formed as the collarinsulating film. Generally, in the DRAM cell with a trench capacitor, acollar insulating film is formed so as to be thinner than a capacitorinsulating film so that an insulating performance is retained between astorage electrode and the semiconductor substrate. The capacitorinsulating film needs to be formed to be thinner than the collarinsulating film in order that a capacity of the trench capacitor may beincreased. As a result, the method disclosed in JP-A-2003-60079 needs tobe applied. However, the above-noted manufacturing method results inmuch trouble and cost increase.

BRIEF SUMMARY OF THE INVENTION

Therefore, an object of the present invention is to provide asemiconductor device in which a manufacturing process can be simplifiedand a method of fabricating the semiconductor device.

The present invention provides a method of manufacturing a semiconductordevice, including forming a trench in a semiconductor substrate, forminga plate diffusion layer in a part of the semiconductor substrateadjacent to the trench, isotropically forming a first insulating film onan entire inside surface of the trench, the first insulating filmincluding a lower portion functioning as a capacitor insulating film,forming a second insulating film on an upper portion of the firstinsulating film by a plasma oxidation so that a thickness of the secondinsulating film is decreased gradually toward a bottom of the trenchafter forming the first insulating film, and forming an electrode layerinside the first-and second insulating films so that the electrode layeris structurally connected to the first and second insulating films.

BRIEF DESCRIPTION OF THE DRAWINGS

Other objects, features and advantages of the present invention willbecome clear upon reviewing the following description of the embodimentwith reference to the accompanying drawings, in which:

FIG. 1 is a schematic sectional view of a semiconductor devicemanufactured by a manufacturing method of one embodiment in accordancewith the present invention, which view being taken along line 1-1 inFIG. 2;

FIG. 2 is a schematic plan view of the semiconductor device;

FIG. 3 illustrates a first step of a process of manufacturing a memorycell;

FIG. 4 illustrates a second step of the memory cell manufacturingprocess

FIG. 5 illustrates a third step of the memory cell manufacturingprocess;

FIG. 6 illustrates a fourth step of the memory cell manufacturingprocess;

FIG. 7 illustrates a fifth step of the memory cell manufacturingprocess;

FIG. 8 illustrates a sixth step of the memory cell manufacturingprocess;

FIG. 9 is a graph showing the relationship between aspect ration and anoxide film thickness;

FIG. 10 illustrates an eighth step of the memory cell manufacturingprocess;

FIG. 11 illustrates a ninth step of the memory cell manufacturingprocess;

FIG. 12 illustrates a tenth step of the memory cell manufacturingprocess;

FIG. 13 illustrates an eleventh step of the memory cell manufacturingprocess;

FIG. 14 illustrates a twelfth step of the memory cell manufacturingprocess;

FIG. 15 illustrates a thirteenth step of the memory cell manufacturingprocess;

FIG. 16 illustrates a fourteenth step of the memory cell manufacturingprocess; and

FIG. 17 illustrates a fifteenth step of the memory cell manufacturingprocess.

DETAILED DESCRIPTION OF THE INVENTION

One embodiment of the present invention will be described with referenceto the accompanying drawings. The invention is applied to a DRAMsemiconductor storage device provided with a DRAM cell (memory cell) ofthe trench capacitor type in the embodiment. FIG. 2 is a schematic planview of a memory cell region of the DRAM semiconductor storage device.FIG. 1 is a schematic sectional view taken along line 1-1 in FIG. 2. Inthe embodiment, a memory cell 3 is formed on a p-type siliconsemiconductor substrate (corresponding to a semiconductor substrate).However, the memory cell 3 may be formed in a p-well region, instead.

<Structure>

Referring to FIG. 2, a DRAM semiconductor storage device 2 as asemiconductor device includes a memory cell region M in which a numberof memory cells 3 are arranged on the silicon semiconductor substrate 1.The memory cells 3 are arranged to be paired and opposed to each otherin a linear symmetry with respect to a bit line BL (shown in FIG. 1).The memory cells 3 are arranged so that the paired memory cells 3 have ahighest degree of integration. An active area AA designates a regionincluding a source/drain diffusion layer of a transistor Tr and achannel region.

Deep trenches 4 (grooves) are provided in a zigzag pattern in the memorycell region M. Each trench 4 is formed into an elliptic shape. Eachmemory cell 3 comprises a trench capacitor C and a metal oxidesemiconductor (MOS) cell transistor Tr as shown in FIG. 1. The trenchcapacitor C is formed so as to be located at a deep part 4 a side ofeach trench 4. A plate diffusion layer 5 is formed outside the trench 4so as to be located at the deep part 4 a side as shown in FIG. 1. Theplate diffusion layer 5 functions as a plate electrode of the trenchcapacitor C. An insulating film 6 is formed on an inner peripheral faceincluding the deep part 4 a side of each trench 4.

A first electrode layer 7 is buried inside the inner peripheral face ofeach trench 4 and the insulating film 6. The first electrode layer 7 ismade from polycrystalline silicon doped with impurities, amorphoussilicon doped with impurities or the like. The first electrode layer 7serves as the other plate electrode (storage node) of the trenchcapacitor C. A second electrode layer 8 is buried over the firstelectrode layer 7 in the trench 4 so as to be in contact with a side ofthe trench 4. The second electrode layer 7 is also made ofpolycrystalline silicon doped with impurities, amorphous silicon dopedwith impurities or the like.

The insulating film 6 is made of a silicon nitrided oxide film (SiN—SiO₂film), Al₂O₃—SiO₂ film, HfO₂—SiO₂ film or the like. The insulating film6 is formed so that a thickness thereof is gradually reduced from thesurface 1 a side of the substrate 1 toward a deep part 4 a side of thetrench 4. In other words, the insulating film 6 is formed so that thethickness thereof is gradually increased from the deep part 4 a side ofthe trench 4 toward the surface 1 a side of the substrate 1. Theinsulating film 6 has a tapered section and includes a part with apredetermined range of height relative to the deep part 4 a of thetrench 4 (for example, a range from 5 to 10 μm, namely, a region asshown by reference symbol L1 in FIG. 1). This part of the insulatingfilm 6 is isotropically formed so as to have a constant film thickness(4 nm, for example) and referred to as “first forming section 6 a.” Thefirst forming section 6 a serves as a capacitor insulating film forseparation of both plate electrodes of the trench capacitor C.

The insulating film 6 is further formed so as to be located over thefirst forming section 6 a. The part located over the first formingsection 6 a is referred to as “second forming section 6 b.” The secondforming section 6 b is formed so as to have a larger thickness than thefirst forming section 6 a. The reason for this is that the first formingsection 6 a is formed in order to increase a capacity of the trenchcapacitor C, whereas the second forming section 6 b is formed in orderto retain the insulation performance between the first and secondelectrode layers 7 and 8 buried in the trench 4 and the siliconsubstrate 1. The second forming section 6 b is formed so that athickness thereof is gradually increased from the lower side toward theupper side. The second forming section 6 b includes a part which islocated on the inner peripheral surface of the trench 4 and has athickness ranging from 30 to 40 nm, for example.

A shallow trench isolation (STI) structure is provided over the firstand second electrode layers 7 and 8 so as to serve as an elementisolation region. As shown in FIG. 1, STI is opposed to the celltransistor Tr relative to the trench 4. An insulating film buried in STIis adapted to electrically separate each trench capacitor C from theadjacent trench capacitors. STI further electrically separates eachtrench capacitor C from a word line WL passing over STI. The secondelectrode 8 is formed over the first electrode 7 in the trench 4 asdescribed above. Thus, the trench capacitor C comprises the first andsecond electrodes 7 and 8, the plate diffusion layer 5 and theinsulating film 6.

The cell transistor Tr is adjacent to the trench capacitor C so as toelectrically be connected to the latter as shown in FIG. 1. A strap 9 isformed on a contact boundary between the cell transistor Tr and thesecond electrode layer 8 buried inside the trench 4. The strap 9 isformed on an upper part of outer periphery of the trench 4 at the celltransistor Tr side by diffusing donor-type impurities outward from thesecond electrode layer 8. The cell transistor Tr comprises a gateelectrode 10 functioning as a word line WL, n-type diffusion layers 11and 12 (source/drain diffusion layers) and a gate oxide film 13 (gateinsulating film). The gate oxide film 13 is formed on the siliconsubstrate 1. The gate electrode 10 comprises a polycrystalline siliconlayer 10 a doped with impurities and formed on the gate oxide film 13and a metal silicide layer 10 b formed on the layer 10 a. The diffusionlayers 11 and 12 are formed on the surface layer side of the siliconsubstrate so as to be located at both ends of the gate electrode 10respectively.

The second electrode layer 8 constituting the trench capacitor C ismechanically in contact with and electrically connected to the diffusionlayer 12. A contact plug 14 is mechanically in contact with andelectrically connected to the other diffusion layer 11. The contact plug14 is provided for electrically connecting the diffusion layer 11 to thebit line BL. Furthermore, an insulating film 15 is formed around thegate electrode 10 so as to cover the gate electrode 10. An interlayerinsulating film 16 is formed between the bit line BL and the memory cell3 to electrically separate the bit line BL and the memory cell 3 fromeach other.

According to the above-described structure, the insulating film 6includes the first formation section 6 a formed on the inner peripheralsurface of the trench 4 at the inner deep portion 4 a side so that thesection 6 a has a uniform film thickness. The insulating film 6 furtherincludes the second formation section 6 b formed so that the thicknessof the section 6 b is gradually increased from the predeterminedlocation between the surface 1 a of the silicon substrate 1 and the deepportion 4 a of the trench 4 toward the surface 1 a side of the siliconsubstrate 1. Accordingly, the insulating film 6 is formed so that thefilm thickness thereof is gradually increased from the deep portion 4 aof the trench 4 toward the surface 1 a side of the silicon substrate 1.The first formation section 6 a functions as the capacitor insulatingfilm of the trench capacitor C, whereas the second formation section 6 bfunctions as a collar insulating film.

In the foregoing embodiment, the second formation section 6 b serving asthe collar insulating film is formed into a tapered shape so that across-sectional area of the electrode layer is increased from the secondelectrode layer 8 toward the first electrode layer 7 at the side of thelower portion of the collar insulating film. As a result, the resistanceof the electrode layer can be rendered lower and accordingly, theoperating speed can be improved. Furthermore, since an upper portion ofthe collar insulating film is tapered, a path through which impuritiesin the first electrode layer 7 leaks to an upper portion can benarrowed. As a result, an amount of impurities entering into the siliconsubstrate 1 side through the second electrode layer 8 can be limited.Consequently, variations in the threshold value of the transistor can belimited, whereupon a memory cell with higher reliability can be formed.Furthermore, since the second formation section 6 b serving as thecollar insulating film is tapered, an upper part of the collarinsulating film is formed on the sidewall of the trench 4 so as to havea larger thickness. Consequently, since impurities in the electrodelayers 7 and 8 are prevented from entering through the collar insulatingfilm into the silicon substrate 1, variations in the threshold value ofthe cell transistor Tr can be limited, whereupon a memory cell withhigher reliability can be formed. Additionally, since the secondformation section 6 b serving as the collar insulating film containsnitrogen (N) atoms, the collar insulating film can be prevented fromheat deterioration, whereby the insulating performance can be improvedbetween the first electrode layer 7 a and the silicon substrate 1.

<Manufacturing Method>

The method of manufacturing the thus configured trench DRAMsemiconductor storage device will now be described with reference toFIGS. 3 to 17. FIGS. 3 to 8 and 10 to 17 are schematic sectional viewsshowing a series of steps of the method of manufacturing the device.Even if the invention can be realized, an order of steps described belowcan be changed at need. One or a plurality of general steps may be addedand one or a plurality of the steps described below may be eliminated.

Firstly, the silicon oxide film 17 is formed on the silicon substrate 1and the silicon nitride film 18 is deposited on the silicon oxide film17, as shown in FIG. 3. Subsequently, a boron silicate glass (BSG) film19 is deposited on the silicon nitride film 18. A tetraethylorthosilicate (TEOS) film 20 serving as a hard mask is further depositedon the BSG film 19.

Photoresist (not shown) for forming a deep trench is applied to the TEOSfilm 20 and then patterned by the photolithography technique as shown inFIG. 4. The silicon oxide film 17, the silicon nitride film 18, the BSGfilm 19 and the TEOS film 20 are etched by an anisotropic etchingprocess, so that the trench 4 is formed. Thereafter, the resist patternis removed by ashing.

Subsequently, as shown in FIG. 5, an anisotropic etching (reactive ionetching (RIE)) is carried out with the BSG and TEOS films 19 and 20serving as masks so that the silicon substrate 1 is etched until apredetermined depth is reached, whereby the deep trench 4 is formed.

After removal of the BSG film 19, arsenic is diffused from inside thetrench 4 over the silicon substrate 1 until a predetermined level(depth) is reached from the deep portion 4 a of the trench 4, wherebythe plate diffusion layer 5 of the trench capacitor C is formed outsidethe trench 4, as shown in FIG. 6. Subsequently, the trench surfaceinsulating film 21 is isotropically formed on the inner surface of thetrench 4 as shown in FIG. 7. The trench surface insulating film 21 ismade from SiN—SiO₂ film, Al₂O₃—SiO₂ film, HfO₂—SiO₂ film or the like. Inthis case, it is desirable that the trench surface insulating film 21should contain nitrogen atom. Subsequently, as shown in FIG. 8, asurface layer side insulating film 22 is formed on an upper part of theinner wall of the trench 4 by plasma oxidation (radical oxidation). Theconditions for the plasma oxidation are as follows: under the conditionsof pressure of 1 Torr, H₂/O₂/Ar=10/10/1000 in sccm and temperature of600° C., the plasma oxidation is carried out at 3.5 kW using anelectromagnetic wave transmitter whose frequency is 2.45 GHz. The unitsccm is an abbreviation of standard cubic centimeter per minute and aunit of flow rate. Although the temperature is set at 600° C. in theembodiment, the surface layer side insulating film 22 with a desiredfilm thickness can be formed by the plasma oxidation when thetemperature ranges from 250° C. to 600° C.

Furthermore, although the plasma oxidation uses a gas with a mixingratio of H₂/O₂/Ar adjusted as described above in the embodiment, a100%-O₂ gas may be used for the plasma oxidation. Additionally, althoughthe plasma oxidation is carried out in the embodiment, plasma nitridingor combination of plasma oxidation and plasma nitriding may be carriedout, instead.

FIG. 9 shows aspect ratio dependency of the film thickness of a filmformed by oxidation when plasma oxidation is carried out for theinterior of the trench 4 using the aforesaid two types of gases. Asobvious from FIG. 9, whichever gas is used, the film thickness of a filmformed by oxidation becomes smaller as an aspect ratio is increased.More specifically, the film thickness of the film formed at a deeplocation in the trench 4 is smaller than the film thickness of the filmformed at a shallow location in the trench 4. Accordingly, the siliconoxide film can be formed from the surface 1 a side of the siliconsubstrate 1 to the deep portion 4 a of the trench 4 so as to becontinuously thin along the inner surface of the trench.

The aspect ratio dependency of the film thickness of a film formed byoxidation becomes higher when a gas with a mixing ratio of H₂/O₂/Ar isused for plasma oxidation than when a 100%-O₂ gas is used for the plasmaoxidation. More specifically, the following results were achieved froman experiment conducted by the inventors. When an oxide film is formedusing an H₂/O₂/Ar gas, the oxide film has a film thickness of 155 Å at adepth of the trench 4 corresponding to the aspect ratio of 0.1. Theoxide film has a film thickness of 80 Å at a depth of the trench 4corresponding to the aspect ratio of 2. Furthermore, the oxide film hasa film thickness of 50 Å at a depth of the trench 4 corresponding to theaspect ratio of 4. See characteristic A in FIG. 9.

On the other hand, when a 100%-O₂ gas is used for the plasma oxidation,the oxide film has a film thickness of 155 Å at a depth of the trench 4corresponding to the aspect ratio of 0.1. The oxide film has a filmthickness of 150 Å at a depth of the trench 4 corresponding to theaspect ratio of 2. Furthermore, the oxide film has a film thickness of145 Å at a depth of the trench 4 corresponding to the aspect ratio of 4.See characteristic B in FIG. 9.

Accordingly, the depth of the trench 4 and the conditions for oxidationare adjusted so that the surface layer side insulating film 22 can beformed so as to be thicker in a portion thereof from the deep portion 4a side of the trench 4 toward the surface 1 a side of the siliconsubstrate 1, as shown in FIG. 8. Furthermore, the film thickness can becontrolled. In this forming step in the embodiment, the surface layerside insulating film 22 is formed so that the film thickness thereofbecomes zero at a middle location in the trench 4 in the direction ofdepth of the trench 4. See a lowermost portion 22 a of the surface layerside insulating film 22 in FIG. 8. When the surface layer sideinsulating film 22 is formed by the aforesaid manufacturing method,crystalline anisotropy is reduced in the boundary between the insulatingfilm 6 and the silicon substrate 1. More specifically, since theinsulating film 6 and the silicon substrate 1 are brought into a planatecontact with each other, electric current leakage due to localconcentration of electric field can be reduced, and the memory cell 3having an improved reliability can be formed.

Subsequently, as shown in FIG. 10, a first polycrystalline silicon layer23 doped with donor impurities is buried inside the trench surfaceinsulating film 21 and surface side insulating film 22 so as to fill theinterior of the trench 4 from the deep portion 4 a to the surface 1 aside of the silicon substrate 1. Subsequently, as shown in FIG. 11, thefirst polycrystalline silicon layer 23 is etched back by the RIE processuntil a predetermined level is reached, whereby the first electrodelayer 7 is formed. In this case, the etchback is carried out so that thelevel below the surface 1 a of the substrate 1 and above the lowermostportion 22 a of the insulating film 22 is reached, whereupon a portionserving as the first electrode layer 7 is formed. In other words, thesurface layer side insulating film 22 is formed so as to be in contactwith an upper side 7 a of the electrode layer 7 upon completion of thestep as shown in FIG. 11.

Subsequently, as shown in FIG. 12, the insulating film 22 formed on thesidewall of the first electrode layer 7 is removed by an isotropicetching process under an etching condition with selectivity for thefirst electrode layer 7. Since a part of the insulating film 22 at thesurface 1 a side is removed in FIG. 12, the remainder of the insulatingfilm 22 is designated by reference symbol “6 b” which indicates thecollar insulating film. In this case, the insulating film 22 formed soas to be in contact with the upper side 7 a of the first electrode layer7 is removed. More specifically, as shown in FIG. 12, the insulatingfilm 22 is removed so that the level below an upper surface of the firstelectrode layer 7 and above the lowermost portion 22 a of the insulatingfilm 22 is reached, whereupon a portion serving as the first electrodelayer 7 is formed. As a result, the portion serving as the collarinsulating film is formed as shown in FIGS. 12 and 13. Next, ions of forexample, Ge and the like are implanted from above the trench 4 for thepurpose of adjustment of a threshold (threshold voltage) of the celltransistor Tr. The resultant impurity diffused layer is not shown.

Subsequently, a second polycrystalline silicon layer 24 doped with donorimpurities is buried on the first electrode layer 7 and the surfacelayer side insulating film 22 (the second formation section 6 b, thecollar insulating film and the collar oxide film) in the trench 4. Thesecond polycrystalline silicon layer 24 is etched back so that a levelbelow the surface 1 a of the substrate 1 and above the upper surface ofthe first electrode layer 7 is reached.

An outer diameter of the trench 4 has recently been reduced and a depththereof has been increased. Accordingly, when the first polycrystallinesilicon layer 23 is buried in the trench 4, the aspect ratio is highsuch that seams (not shown) are formed in the second polycrystallinesilicon layer 24. In the embodiment, however, the collar insulating film(the second formation section 6 b) can be formed on the upper surface 7a of the first electrode layer 7 without forming an insulating film onthe electrode layer 7. Consequently, no insulating film is buried in theseams. In a conventional method, an insulating film is isotropicallyformed in the trench 4 before the second polycrystalline silicon layer24 is buried on the upper side 7 a (see FIG. 12) of the first electrodelayer 7. Only the insulating film formed on the first electrode layer 7is removed by the RIE process so that the insulating film remains on thesidewall of the trench 4. The method of the embodiment can form thesemiconductor storage device without the aforesaid step of removing theinsulating film and accordingly reduce the costs as compared with theabove-described conventional method.

Moreover, a good electrical connection can be obtained between the firstelectrode layer 7 and the second polycrystalline silicon layer 24 sinceno insulating film is formed between these layers 7 and 24.Consequently, an increase in a contact resistance value can be preventedand failure in write can be reduced. Furthermore, the insulating film 22is formed at a low temperature before the second polycrystalline siliconlayer 24 is buried in the first electrode layer 7. Consequently, outwarddiffusion of the donor impurities such as arsenic (As) from the firstelectrode layer 7 (the first polycrystalline silicon layer 23) can beprevented and accordingly, a profile control of the diffusion layer caneasily be carried out and accordingly, the memory cell 3 with highreliability can be formed. Additionally, the electrode layer is buriedin the trench 4 only twice in the embodiment although the electrodelayer needs to be buried in the trench three times in the conventionalmethod.

Subsequently, resist (not shown) is applied so that a resist pattern isformed by the photolithography technique. Thereafter, as shown in FIG.13, a groove 25 is formed in the silicon substrate 1, the firstelectrode layer 7, the second polycrystalline silicon layer 24 and theinsulating film 6 b by the anisotropic etching process. Subsequently,the TEOS film 26 is deposited as shown in FIG. 14. Furthermore, as shownin FIG. 15, the TEOS film 26 is etched back so that a level near thesurface 1 a of the silicon substrate 1 is reached, whereby the siliconnitride film 18 used as a hard mask for forming the trench 4 and thesilicon oxide film 17 are removed. Next, the silicon oxide film 13serving as a gate insulating film is formed on the silicon substrate 1.

Subsequently, as shown in FIG. 16, a high temperature heat treatment iscarried out so that the donor impurity (phosphor, arsenic or the like,for example) is diffused outward thereby to be formed into the strap 9.The strap 9 is provided for reducing electrical resistance between thediffusion layer 12 of the cell transistor Tr and the trench capacitor C.Subsequently, as shown in FIG. 17, the gate electrodes 10 of the celltransistor Tr are formed on the silicon oxide film 13 and the STI. Thesource/drain diffusion layers 11 and 12 are formed on the opposite sidesof each gate electrode 10 at the surface layer side of the siliconsubstrate 1. Further, the sidewall insulating film 15 is formed on thesidewall of each gate electrode 10. In this case, the diffusion layer 12of the cell transistor Tr is formed so as to be electrically connectedto the second electrode layer 8.

Subsequently, as shown in FIG. 1, the interlayer insulating film 16 isburied on the sidewall insulating film 15 formed on the sidewall of eachgate electrode 10. The interlayer insulating film 16 is then etched sothat a part of the interlayer insulating film 16 on the diffusion layer11 composing the cell transistor Tr is removed, whereby a contact hallis formed. A barrier metal layer (not shown) and an electrode layer (notshown) are formed in the contact hall, whereby the contact plug 14 isformed.

Subsequently, the bit line BL serving as upper layer winding comprisinga titan (Ti) film, tungsten (W) film and the like is formed on thecontact plug 14. As a result, the contact plug 14 electrically connectsthe diffusion layer 11 and the bit line BL together.

According to the above-described manufacturing method, the trenchsurface insulating film 21 is isotropically formed so as to extend fromthe surface 1 a side of the silicon substrate 1 toward the deep portion4 a of the trench 4. The trench surface insulating film 21 is furtherformed so that the first formation section 6 a at the deep portion 4 aside serves as the capacitor insulating film. The plasma oxidation andplasma nitriding are carried out so that the trench surface insulatingfilm 21 is rendered thin continuously from the surface 1 a side of thesilicon substrate 1 toward the deep portion 4 a of the trench 4 in thetrench 4, whereby the surface side insulating film 22 is formed. Thefirst polycrystalline silicon layer 23 (electrode layer) is buriedinside the insulating films 21 and 22 both formed on the inner surfaceof the trench 4. The first polycrystalline silicon layer 23 is thenetched back so that the first electrode layer 7 is formed.

According to the foregoing embodiment, even when seams (not shown) areformed in the first electrode layer 7, the second formation section 6 bas the collar insulating film can be formed on the upper inner sidewallof the trench 4 without an insulating film on the first electrode layer7. Consequently, the memory cell 3 of the trench DRAM can readily beformed. Moreover, since the memory cell can be configured without anyinsulating film on the first electrode layer 7, the electrical contactresistance can be restrained between the first and second electrodelayers 7 and 8.

In a modified form of the embodiment, the invention is applied to thep-type silicon substrate in the foregoing embodiment. However, any typeof semiconductor substrate may be used. In another modified form, theinvention may be applied to a general purpose DRAM, custom DRAM or anydevice having a DRAM area together with another circuit area.

The foregoing description and drawings are merely illustrative of theprinciples of the present invention and are not to be construed in alimiting sense. Various changes and modifications will become apparentto those of ordinary skill in the art. All such changes andmodifications are seen to fall within the scope of the invention asdefined by the appended claims.

1. A semiconductor device comprising: a semiconductor substrate; atrench formed in the substrate; an insulating film formed on an innersurface of the trench so as to be rendered thicker from a substratesurface side thereof toward a trench deep side thereof; and an electrodelayer formed inside the insulating film formed inside the trench so asto extend from a trench deep part side toward the surface side of thesubstrate, wherein the substrate surface side of the insulating filmfunctions as a collar insulating film retaining an insulationperformance between the electrode layer and the semiconductor substrate,and the trench deep side of the insulating film functions as a capacitorinsulating film composing a capacitor of a DRAM cell.
 2. Thesemiconductor device according to claim 1, wherein the insulating filmis formed so as to have a tapered section and contains a nitrogen atom.